The present invention relates to image display devices and to driver circuits therefor. More particularly, the invention relates to an active-matrix type of display device with built-in pixel circuits, the display device further having a driver circuit on a substrate and reducing an area of a non-display region, and to the driver circuit.
Electroluminescent (EL) displays that use EL elements are reported as the image display devices that use light-emitting elements to form pixels. Active-matrix types of EL displays further contain pixel circuits, each of which includes wiring routed in matrix form to transmit signals and electric currents and employs, in addition to EL elements, thin-film transistors (TFTs) that are active elements, to form pixels.
Pixel circuits control the light-emitting luminance of EL elements by controlling electric currents which the pixel circuits are to supply to the EL elements. A method of controlling currents by using pixel circuits is reported in Japanese Patent Laid-Open No. 2003-122301 (refer to Patent Document 1). Also, organic EL diodes are known as EL elements whose light-emitting luminance changes in proportion to the amount of current.
The circuit composition of a conventional pixel circuit PX which uses an EL element is shown in FIG. 17A. A pixel circuit PX equivalent to that of FIG. 17A is shown in simplified form in FIG. 17B. These pixel circuits PX include a data line D for transmitting an image signal voltage VD, a gate line G for transmitting a scanning pulse, a triangular-wave signal line S for transmitting a triangular-wave voltage waveform Vs, TFTs_Q1 to Q3 each functioning as a switch, a p-channel TFT_Q4 for controlling a current, and a capacitor C. Although an EL element 51 and a grounding electrode 52 are also shown in FIGS. 17A and 17B, these two elements are, as a matter of fact, created in overlapped form by vapor-depositing a light-emitting organic film and common electrode not shown. A current IOLED that flows into the EL element is supplied from a power supply line 53, then passed through the TFT_Q4 and the EL element 51, and flows into the grounding electrode 52. The light-emitting intensity of the EL element 51 is proportionate to a time-varying integral quantity of current IOLED flowing during a vertical scanning period.
The relationship between the logical state of the gate line G and the ON/OFF operation of the TFTs_Q1 to Q3 is shown in FIG. 18. When the gate line G is at a high (H) level, the TFTs_Q1 and Q2 are active (ON) and the TFT_Q3 is inactive (OFF). Under this state, the pixel circuit PX reads the image signal voltage VD of the data line D into the capacitor. When the gate line G is at a low (L) level, the TFTs_Q1 and Q2 are OFF and the TFT_Q3 is ON. Under this state, the pixel circuit 13 compares the triangular-wave voltage waveform VS and the voltage which the pixel circuit has read into the capacitor, and depending on the relationship in magnitude between both voltages, controls whether the current IOLED is to be conducted (supplied).
The principles of operation of the pixel circuit PX when it controls the brightness of the EL element 51 by using the image signal voltage VD are described hereunder.
FIG. 19 shows examples of operation waveforms of each section in the pixel circuit PX of FIG. 17A. A pulse is supplied to the gate line G with each arrival of the vertical scanning period TV. When the pulse is input to the gate line G (i.e., when G takes level H), the voltage VD of the data line D is read into the capacitor C. A voltage VC of a node located to the left of the capacitor C takes the same value as that of the then voltage VD of the data line D. At the same time, when Q1 turns ON, a voltage VX developed at the right side of the capacitor C becomes a voltage VRES used as a threshold of a criterion for the TFT_Q4 to judge whether it is to conduct the current IOLED. When a pulse is not input to the gate line G (i.e., when G takes level L), the voltage waveform VS of the triangular-wave signal line S is applied to the capacitor C and the voltage VC of the node located to the left of the capacitor C takes the same waveform as the triangular-wave voltage waveform VS. When the triangular-wave voltage is high in comparison with the voltage VD of the data line D at level H of the gate line G, the TFT_Q4 is in an OFF state and the current IOLED is not flowing. Conversely, when the triangular-wave voltage is low in comparison with the voltage VD of the data line D at level H of the gate line G, the TFT_Q4 is in an ON state and the current IOLED is flowing.
An example in FIG. 19 shows a relatively low voltage VDL as the image signal voltage VD of the data line at time “t1”. The voltage VDL is read into the capacitor C in synchronization with the pulse of the gate line G. During a period from time “t1” to time “t2”, although the triangular-wave voltage waveform VS is supplied to the node located to the left of the capacitor, the voltage that the capacitor C holds between electrodes causes the node voltage VX at the right side of the capacitor to take a waveform obtained by shifting the voltage waveform of the voltage VC so that a relatively high VC voltage value is obtained. Accordingly, an integral quantity of current IOLED flowing during the vertical scanning period TV relatively decreases and the EL element 21 looks relatively dark.
Another example in FIG. 19 shows a relatively high voltage VDH as the image signal voltage VD of the data line at time “t2”. The voltage VDH is read into the capacitor C in synchronization with the pulse of the gate line G. During a period from time “t2” to time “t3”, although the triangular-wave voltage waveform VS is supplied to the node located to the left of the capacitor, the voltage that the capacitor C holds between electrodes causes the node voltage VX at the right side of the capacitor to take a waveform obtained by shifting the voltage waveform of the voltage VC so that a relatively low VC voltage value is obtained. Accordingly, an integral quantity of current IOLED flowing during the vertical scanning period TV relatively increases and the EL element 21 looks relatively bright. The composition and driving principles of the pixel circuit are described in further detail in Japanese Patent Laid-Open No. 2003-005709 (refer to Patent Document 2).
As described above, an image display device can be created by forming on a substrate a matrix-form array of pixel circuits each capable of controlling the brightness of an EL element by using an image signal voltage VD.
A configuration of a conventional image display device created using pixel circuits PX is shown in FIG. 20. A plurality of pixel circuits PX are arranged in matrix form in an image display region 62 on the surface of a transparent glass substrate 60. Data driver LSI 64, a scanning circuit 65, and signal generators (S_GENE) 66 to 69 are arranged around the display region 62. An output of the scanning circuit 65 is connected to each pixel circuit PX via gate lines G1 to G4, and an output of the data driver LSI 64 is connected to each pixel circuit PX via a data line 75. Outputs of the signal generators 66 to 69 are connected to the respective pixel circuits PX through triangular-wave signal lines S1 to S4. In synchronization with pulses of the gate lines G1 to G4, the signal generators 66 to 69 generate V-shaped triangular-wave voltage waveforms VS1, to VS4, respectively, that differ from one another in terms of phase.
In FIG. 20, only five pixel circuits PX, one in an X-direction and four in a Y-direction, are shown for a better understanding of description. A general image display device, however, has at least several hundreds of pixel circuits arrayed in both X- and Y-directions. These pixel circuits PX take the circuit composition shown in FIG. 17A. A shift register circuit composed of multiple latches is used as a scanning circuit 65. Although the number of latches in the scanning circuit 65 and the number of signal generators 66 to 69 are both four in FIG. 20, the actual number of these elements is the same as used in the Y-direction of the pixel circuit composition.
FIG. 21 shows the voltage waveforms that data driver LSI 64, scanning circuit 65, and signal waveform generators 66 to 69 generate. The data driver LSI 64 sequentially outputs image signal voltages VD1 to VD4 to a data line 75, and the scanning circuit 65 outputs a pulse signal Sync to gate lines G1 to G4 in synchronization with the image signal voltages VD1 to VD4. Since the signal generators (S_GENE) 66 to 69 each supplying a triangular wave synchronously with the pulse signal that the scanning circuit 65 generates are provided, the signal generators 66 to 69 generate triangular-wave voltage waveforms VS1 to VS4, respectively, that differ from one another in terms of phase. Hence, synchronization between the pulse signal and the triangular-wave voltage waveform can be obtained over an entire vertical scanning period TV in all pixel circuits PX.
All pixel circuits can operate as shown in FIG. 19. One method of realizing the signal generators 66 to 69 is by using such integrators that are reported per FIGS. 7 and 10 of Japanese Patent Laid-Open No. 2004-510208.
[Patent Document 1]
Japanese Patent Laid-Open No. 2003-122301
[Patent Document 2]
Japanese Patent Laid-Open No. 2003-005709
[Patent Document 3]
Japanese Patent Laid-Open No. 2004-510208